Title :
Overcoming bottlenecks in high-speed transport systems
Author :
Siegel, Martin ; Williams, Mark ; Rossler, G.
Author_Institution :
Inst. for Commun. Switching & Data Technics, Stuttgart Univ., Germany
Abstract :
An architecture is presented for HSLAN/MAN controllers. This front-end processor system (FEP) is designed for operation in a CLN/LLC 1 environment, and implements the ISO OSI TP4 transport protocol. The FEP uses one or more commercial microprocessors with layers 2b-4 implemented in firmware. The protocol processors are supported by custom VLSI hardware such as a checksummer, DMA units, and process coupling devices as required. Layers 1 and 2a are provided by commercial chipsets. The FEP is optimised for a LAN/MAN environment while allowing the host to communicate over wide-area networks. It is general enough to be adapted to non-OSI protocol suites. Initial estimates indicate that the FEP should be able to transmit and receive at full FDDI bandwidth with a TPDU length of 1k octets
Keywords :
local area networks; open systems; protocols; satellite computers; CLN/LLC 1 environment; DMA units; FDDI bandwidth; HSLAN/MAN controllers; ISO OSI TP4 transport protocol; TPDU length; VLSI hardware; checksummer; firmware; front-end processor system; high-speed transport systems; microprocessors; process coupling devices; wide-area networks; Bandwidth; FDDI; Hardware; ISO; Local area networks; Microprocessors; Microprogramming; Open systems; Transport protocols; Very large scale integration;
Conference_Titel :
Local Computer Networks, 1991. Proceedings., 16th Conference on
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-8186-2370-5
DOI :
10.1109/LCN.1991.208092
