Title :
Self-reconstruction of mesh-arrays with 1½-track switches by digital neural circuits
Author :
Takanami, Itsuo ; Horita, Tadayoshi
Author_Institution :
Dept. of Comput. Sci., Iwate Univ., Morioka, Japan
Abstract :
Previously, we have proposed the Hopfield-type neural algorithm for reconstructing mesh-connected processor arrays using single-track switches and mentioned that the algorithm could be realized by hardware where the algorithm requires four neurons for each processor element (PE) in order to decide compensation paths for faulty PEs under the constraints. This paper shows how the algorithm can be realized by a digital neural circuit. It consists of subcircuits for finding candidate compensation paths, deciding whether the neural system reaches a stable state and at the time the system energy is minimum, and subcircuits for neurons. The subcircuit for each neuron can only be made with 17 gates and two flip-flops. Since the state transitions are done in parallel, the circuit will be able to find the compensation paths for a fault pattern very quickly within a time less than 1 μs
Keywords :
CMOS digital integrated circuits; Hopfield neural nets; VLSI; fault tolerant computing; integrated circuit reliability; microprocessor chips; parallel architectures; reconfigurable architectures; 1½-track switches; Hopfield-type neural algorith; compensation paths; digital neural circuits; mesh-connected processor arrays; parallel state transitions; self-reconstruction; stable state; subcircuits; CMOS technology; Circuit faults; Concurrent computing; Hardware; Neural networks; Neurons; Semiconductor device modeling; Switches; Switching circuits; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1997. Proceedings., 1997 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
0-8186-8168-3
DOI :
10.1109/DFTVS.1997.628328
