Fast error-correcting Newton-Raphson dividers using time shared TMR

Many implementations of division are based on the Newton-Raphson method, as it quickly converges to a solution and can often utilize a multiplier that is already on chip. Applying time shared triple modular redundancy (TSTMR) to such a divider allows the use of a smaller multiplier and requires triplicating the divider circuit. The smaller multiplier completes larger multiplications in several cycles using feedback registers. While this reduces the size of the fault tolerant divider over that of traditional TMR, there is a substantial penalty to latency. However, because early stages of the algorithm do not require high-precision multiplications, and rounding the quotient by computing the inverse function does not require a full-precision multiplication, the algorithm can be modified to reduce multiplication cycles. The resulting error-correcting dividers can be both faster and smaller than fault-tolerant dividers using traditional TMR