Title :
Designing networks with error detection properties through the fault-error relation
Author :
Bolchini, Cristiana ; Salice, Fabio ; Sciuto, Donatella
Author_Institution :
Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
Abstract :
The paper proposes an approach for designing TSC networks by means of error detecting code application, based on the analysis of the desired fault-error relation. The network structure is analyzed by taking into account each possible fault, belonging to the adopted fault set, and by verifying if the produced error is detectable with respect to the adopted encoding. If undetectable faults are located the network is locally modified, so that area overheads for TSC designs are limited
Keywords :
VLSI; automatic testing; digital integrated circuits; error detection; error detection codes; integrated circuit testing; logic design; logic testing; observability; TSC network design; error detecting code application; error detection properties; fault set; fault-error relation; totally-self-checking network; Circuit faults; Circuit synthesis; Circuit testing; Design methodology; Electrical fault detection; Encoding; Fault detection; Fault diagnosis; Network synthesis; Observability;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1997. Proceedings., 1997 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
0-8186-8168-3
DOI :
10.1109/DFTVS.1997.628336
