Title :
A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing
Author :
Srinivasan, Rajagopalan ; Njinda, Charles A. ; Breuer, Melvin A.
Author_Institution :
Dept. of Electr. Eng., Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
Pseudo-exhaustive testing of combinational circuits usually requires multiple test sessions and/or more than a minimum number of test signals, i.e. unique input sequences. This paper presents a methodology for partitioning combinational circuits such that they can be pseudo-exhaustively tested with a minimal number of test signals in a single test session. Circuits are logically partitioned during test mode and unrelated inputs are combined to achieve maximal test concurrency.<>
Keywords :
combinatorial circuits; logic testing; combinational circuits; maximal test concurrency; partitioning method; pseudo-exhaustive testing; single test session; test mode; test signals; unrelated inputs; Circuit faults; Circuit testing; Combinational circuits; Concurrent computing; Contracts; Government; Logic testing; Monitoring; System testing; Upper bound;
Conference_Titel :
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location :
Atlantic City, NJ, USA
DOI :
10.1109/VTEST.1991.208129
