Title :
Compact testing with intermediate signature analysis
Author_Institution :
Dept. of Comput. Sci., North Texas Univ., Denton, TX, USA
Abstract :
Among a number of techniques for efficiently testing VLSI circuits, the BIST using compression technique is recognized as reliable and cost effective. While compact testing using signature analysis allows an efficient test, some faulty responses cannot be detected due to aliasing. This paper shows how the aliasing probability can be significantly reduced by a factor of 2/sup (k+1)/ when k intermediate signatures are checked. The proposed scheme can also quickly detect the fault using fewer hardware resources.<>
Keywords :
VLSI; built-in self test; fault location; integrated logic circuits; logic testing; BIST; VLSI; aliasing; compression technique; hardware resources; intermediate signature analysis; intermediate signatures; probability; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Electrical fault detection; Fault detection; Hardware; Integrated circuit technology; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location :
Atlantic City, NJ, USA
DOI :
10.1109/VTEST.1991.208131
