DocumentCode
3116300
Title
Combining IEEE Standard 1149.1 with reduced-pin-count component test
Author
Oakland, Steven F.
Author_Institution
IBM Gen. Technol. Div., Essex Junction, VT, USA
fYear
1991
fDate
15-17 April 1991
Firstpage
78
Lastpage
84
Abstract
This paper describes a boundary-scan structure that permits comprehensive testing of level-sensitive-scan design (LSSD) components with high signal input/output (I/O) pin counts, using relatively inexpensive reduced-pin-count automatic testing equipment (ATE). Furthermore, the structure conforms to IEEE Standard 1149.1, Test Access Port and Boundary-Scan Architecture, which simplifies testing of assembled printed-circuit boards or other multi-component substrates.<>
Keywords
VLSI; automatic test equipment; logic testing; standards; IEEE Standard 1149.1; Test Access Port; automatic testing equipment; boundary-scan structure; level-sensitive-scan design; printed-circuit boards; reduced-pin-count component test; Assembly; Automatic testing; Circuit testing; Clocks; Cost function; Integrated circuit interconnections; Pins; System testing; USA Councils; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location
Atlantic City, NJ, USA
Type
conf
DOI
10.1109/VTEST.1991.208137
Filename
208137
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