Aspects on integration of high-speed multiplexers and demultiplexers in VLSI test systems

Author

Chowanetz, M. ; Kuntzsch, C. ; Wolz, W.

Author_Institution

Inst. of Comput.-Aided Circuit Design, Erlangen-Nurnberg Univ., Germany

fYear

1991

fDate

15-17 April 1991

Firstpage

128

Lastpage

133

Abstract

The authors describe hardware and software solutions for the design of a high-speed tester channel. Using gallium-arsenide circuitry for the merging of tester pin waveforms, cycle periods of less than 1 ns have been achieved. Hardware design alternatives are discussed, and a scheme for the automatic generation of tester-readable pattern description files is introduced. The conversion algorithms that allow for this generation are described.<>

Keywords

VLSI; automatic test equipment; integrated circuit testing; multiplexing equipment; 1 ns; ATE; VLSI test systems; automatic generation; conversion algorithms; cycle periods; demultiplexers; high-speed multiplexers; high-speed tester channel; tester-readable pattern description files; Accuracy; Circuit testing; Clocks; Consumer electronics; Electronic equipment testing; Hardware; Multiplexing; System testing; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers

Conference_Location

Atlantic City, NJ, USA

Type

conf

DOI

10.1109/VTEST.1991.208142

Filename

208142

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3116434