On hot-carrier induced degradation, temperature, bias and emitter geometry dependences of the DC characteristics of polysilicon-emitter bipolar transistors

The hot-carrier induced degradation, temperature, bias and emitter geometry dependences of the DC characteristics of polysilicon-emitter NPN BJTs have been systematically investigated. We have identified various current components, such as the diffusion, SRH recombination/generation, Poole-Frenkel high field-assisted generation, and trap-assisted tunneling currents, in the forward and reverse base-emitter currents under different conditions. Those conduction mechanisms involving mid-gap trap states become to dominate as more traps and damage are generated after reverse-bias stressing. The origin of induced device degradation by either scaling down device dimension, lowering temperature or stressing is located in the same region as where the hot-carriers are injected during stressing - around the emitter perimeter.