Title :
High accelerated lifetime test methods and procedures for VLSI microcircuit interconnection line certification
Author :
Weis, E.A. ; Kinsbron, E. ; Chanoch, G. ; Snyder, M.M.
Author_Institution :
Fac. of Eng., Tel-Aviv Univ., Ramat Aviv, Israel
Abstract :
As an outcome of the advances in integrated circuit fabrication technology, electromigration has become a major reliability concern in silicon VLSI circuits. This paper represents an innovative testing approach, that allows a substantial reduction in the electromigration test times of metal thin films, and can be implemented as an in-line process electromigration monitor.<>
Keywords :
VLSI; circuit reliability; electromigration; integrated circuit testing; life testing; metallisation; Si; VLSI microcircuit; electromigration; fabrication technology; in-line process monitor; interconnection line certification; lifetime test methods; metal thin films; reliability; Circuit testing; Electromigration; Fabrication; Integrated circuit reliability; Integrated circuit technology; Life estimation; Lifetime estimation; Silicon; Thin film circuits; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location :
Atlantic City, NJ, USA
DOI :
10.1109/VTEST.1991.208144
