DocumentCode
3116519
Title
A software system architecture for testing multiple part number wafers
Author
Smyczynski, R.M. ; Brennan, K.
Author_Institution
IBM Corp., Hopewell Junction, NY, USA
fYear
1991
fDate
15-17 April 1991
Firstpage
134
Lastpage
136
Abstract
Testing single part number wafers is the normal mode of testing semiconductor devices in the industry today. However, as wafers get larger it may become more economical to put different devices on the same wafer resulting in multiple part number wafers. The authors describe a system architecture that allows for the testing of such wafers.<>
Keywords
automatic testing; electronic engineering computing; integrated circuit manufacture; integrated circuit testing; production testing; multiple part number wafers; semiconductor devices; software system architecture; testing; Computer architecture; Control systems; Debugging; Environmental economics; Manufacturing systems; Semiconductor device testing; Semiconductor devices; Software systems; Software testing; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location
Atlantic City, NJ, USA
Type
conf
DOI
10.1109/VTEST.1991.208147
Filename
208147
Link To Document