An analysis and testing of operation induced faults in MOS VLSI

Author

Rajsuman, R. ; Jayasumana, A.P. ; Malaiya, Y.K. ; Park, J.

Author_Institution

Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA

fYear

1991

fDate

15-17 April 1991

Firstpage

137

Lastpage

142

Abstract

The operation induced faults in CMOS circuits are discussed. The significance of these faults for high density, small geometry circuits is pointed out. For modeling purposes the effects of these faults are correlated with classical fault models. A conductance fault model is presented to incorporate these faults. A test scheme to detect these faults is suggested which is based on the measurement of supply current. A scheme to generate test patterns for these faults is also outlined.<>

Keywords

CMOS integrated circuits; VLSI; fault location; integrated circuit testing; semiconductor device models; CMOS circuits; MOS VLSI; conductance fault model; high density circuits; internal latch-up; measurement; operation induced faults; small geometry circuits; supply current; test pattern generation; testing; Circuit faults; Circuit testing; Current measurement; Current supplies; Electrical fault detection; Fault detection; Geometry; Semiconductor device modeling; Test pattern generators; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers

Conference_Location

Atlantic City, NJ, USA

Type

conf

DOI

10.1109/VTEST.1991.208148

Filename

208148