DocumentCode
3116543
Title
Modeling the effects of imperfect production testing on reconfigurable VLSI chips
Author
Ciciani, B.
Author_Institution
Dept. of Electron. Eng., Roma Univ., Italy
fYear
1991
fDate
15-17 April 1991
Firstpage
143
Lastpage
148
Abstract
An innovative method for the ´apparent´ yield evaluation is presented. By this method it is possible to evaluate the quality of the manufacturing process and the expected fraction of truly good chips at the end of the testing and reconfiguration phase. It permits the characterization of fault-tolerant VLSI chips (or WSI systems) with and without redundancy. It is easy to use and permits the predictability of the approximation level of the yield values.<>
Keywords
VLSI; circuit reliability; integrated circuit testing; production testing; quality control; redundancy; WSI systems; fault-tolerant VLSI chips; imperfect production testing; manufacturing process; modelling; reconfigurable VLSI chips; redundancy; yield evaluation; Circuit faults; Circuit testing; Electronic equipment testing; Fault detection; Fault tolerance; Fault tolerant systems; Manufacturing processes; Production; Redundancy; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location
Atlantic City, NJ, USA
Type
conf
DOI
10.1109/VTEST.1991.208149
Filename
208149
Link To Document