Title :
Floorplanning of hierarchical layout in ASIC environment
Author :
Modarres, Hossein ; Raam, Susan ; Lai, Jiun-Hao
Author_Institution :
LSI Logic Corp., Milpitas, CA, USA
Abstract :
A description is given of a novel floorplanning approach which can be used in implementing designs which are defined in a hierarchical manner. Design-specific constraints are communicated to the floorplanner through a hierarchical structure. The approach can then be applied to automatically floorplan the chip while taking performance and feasibility issues into account simultaneously
Keywords :
VLSI; circuit layout CAD; integrated logic circuits; monolithic integrated circuits; ASIC environment; CAD; VLSI; feasibility; floorplanning; hierarchical layout; integrated logic circuit; monolithic IC; Application specific integrated circuits; Automatic control; Delay effects; Design optimization; Functional programming; Integrated circuit interconnections; Large scale integration; Logic design; Monte Carlo methods; Shape;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20815
