Title :
Enhanced fault modeling for DRAM test and analysis
Author :
Oberle, H.-D. ; Maue, M. ; Muhmenthaler, P.
Author_Institution :
Siemens AG Semicond. Group, Munchen, Germany
Abstract :
For typical physical DRAM cell array defects, logical fault models are derived. These models completely and unambiguously describe all coupling faults and pattern sensitivities. Thus, test patterns are developed for production tests and fault analyses with high fault coverage.<>
Keywords :
DRAM chips; cellular arrays; fault location; integrated circuit testing; production testing; DRAM; cell array defects; coupling faults; fault analyses; fault modeling; high fault coverage; logical fault models; pattern sensitivities; production tests; test patterns; Capacitors; Circuit faults; Circuit testing; Logic arrays; Modems; Mutual coupling; Pattern analysis; Production; Random access memory; Switches;
Conference_Titel :
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location :
Atlantic City, NJ, USA
DOI :
10.1109/VTEST.1991.208150
