Title :
On polynomial-time testable classes of combinational circuits
Author :
Rao, Nageswara S V ; Toida, Shunichi
Author_Institution :
Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA
Abstract :
The problem of test generation for detecting stuck-at faults in combinational circuits is computationally intractable. Consequently, the identification of classes of circuits that support polynomial-time test generation algorithms is very important from testing and design viewpoints. The authors discuss several classes of polynomially-time testable circuits. First, they consider the existing polynomial classes obtained by using decompositions of the circuits. Another type of decomposition is proposed, based on fanout-reconvergent pairs, which also lead to classes of polynomial-time testable circuits. Then, the authors present the classes of polynomial-time testable circuits that are formed by the Boolean formulae belonging to the classes of weakly positive, weakly negative, bijunctive and affine.<>
Keywords :
Boolean algebra; combinatorial circuits; computational complexity; logic testing; polynomials; Boolean formulae; NP complete problem; combinational circuits; fanout-reconvergent pairs; polynomial-time testable classes; stuck-at faults; test generation; Algorithm design and analysis; Circuit testing; Combinational circuits; Computer science; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Polynomials; Sequential analysis;
Conference_Titel :
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location :
Atlantic City, NJ, USA
DOI :
10.1109/VTEST.1991.208154