DocumentCode
3116721
Title
Thermal mechanical modeling and assessment for a novel power system module with vertical input capacitor
Author
Qian, Richard ; Liu, Yumin ; Liu, Yong ; Martin, Steve ; Jeon, O.S.
Author_Institution
Fairchild Semicond. Corp, South Portland, ME, USA
fYear
2011
fDate
18-20 April 2011
Firstpage
42377
Lastpage
42590
Abstract
In this paper, a novel power system module (PSM) is developed by integrating the vertical input capacitor inside the package. Comparing with the traditional PSM, the novel PSM has better electrical performance with less parasitic inductance and switching loss, due to a small loop from the input capacitor to the MOSFETs. A comprehensive modeling study is carried out to assess the assembly stress, thermal performance and reliability performance of the novel PSM. The impact of input capacitor height of the novel PSM is studied by building models with different input capacitor height designs. The modeling of the traditional PSM without the input capacitor is also conducted for comparison. The molding cure process is simulated to study the thermal stress induced by the CTE mismatch of different materials. The non-linear elastic plastic material constitutive model is applied to solder, clip and lead frame. The stress on die, solder paste and solder bump is evaluated and analyzed. Thermal characterization of all the package models is conducted to calculate the thermal resistance Rthja according to the JEDEC standards. The matrix method is used to obtain the thermal resistance of all dies, by applying power on different dies separately. The reliability performance is simulated and compared for all package models, including the autoclave (ACLV) test and preconditioning test. An equivalent CTE method is used to simulate the total stress after the ACLV and reflow process, including the hygroscopic stress, vapor pressure induced stress, and the CTE mismatch induced stress. Finally, the possible failure modes of the novel PSM are discussed.
Keywords
MOSFET; capacitors; circuit reliability; electronics packaging; modules; plastics; solders; thermal resistance; JEDEC standards; MOSFET; autoclave test; die; hygroscopic stress; molding cure process; nonlinear elastic plastic material; package models; parasitic inductance; power system module; reflow process; reliability; solder bump; solder paste; switching loss; thermal mechanical modeling; thermal resistance; thermal stress; vapor pressure induced stress; vertical input capacitor; Analytical models; Capacitors; Integrated circuit modeling; Lead; Leg; MOSFET circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2011 12th International Conference on
Conference_Location
Linz
Print_ISBN
978-1-4577-0107-8
Type
conf
DOI
10.1109/ESIME.2011.5765805
Filename
5765805
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