DocumentCode :
3116734
Title :
A substructure method for strip level warpage simulation of a power module in assembly process
Author :
Gu, Jianghai ; Liang, Lihua ; Liu, Yong
Author_Institution :
Fairchild-ZJUT Joint Lab., Zhejiang Univ. of Technol., Hangzhou, China
fYear :
2011
fDate :
18-20 April 2011
Firstpage :
42376
Lastpage :
42558
Abstract :
A substructural method is developed to simulate the strip level warpage of a power module in assembly process. The comparison between substructure and non-substructure methods is presented and discussed. Parametric design of experimental (DoE) study on low side (LS) and high side (HS) die thickness, epoxy mold compound (EMC) thicknenss, as well the Young´s modulus Ez of prepreg and Young´s modulus of EMC is conducted in the simulation.
Keywords :
Young´s modulus; design of experiments; multichip modules; power supply circuits; Young modulus; assembly process; design of experiments; epoxy mold compound; multichip modules; power module; strip level warpage simulation; Copper; Electromagnetic compatibility; Load modeling; Strips; Three dimensional displays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2011 12th International Conference on
Conference_Location :
Linz
Print_ISBN :
978-1-4577-0107-8
Type :
conf
DOI :
10.1109/ESIME.2011.5765806
Filename :
5765806
Link To Document :
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