DocumentCode
3116801
Title
STarS: a target switching algorithm for sequential test generation
Author
Heap, Mark A. ; Rogers, William A. ; Burns, William B.
Author_Institution
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fYear
1991
fDate
15-17 April 1991
Firstpage
210
Lastpage
215
Abstract
The authors introduce a new deterministic test pattern generation algorithm for sequential circuits. The Sequential Target Switching (STarS) algorithm begins generating a test sequence for a specific target fault, but as each pattern is generated, it keeps track of the set of faults that may also use this sequence as part of a test. Backtracking is avoided by switching the target fault to a member of this fault set, and partial sequences are re-used as much as possible.<>
Keywords
automatic testing; fault location; logic testing; sequential circuits; sequential switching; STarS; deterministic test pattern generation algorithm; fault set; partial sequences; sequential circuits; sequential test generation; target switching algorithm; Circuit faults; Circuit testing; Iterative algorithms; Logic testing; Power generation; Sequential analysis; Sequential circuits; Space exploration; Switches; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location
Atlantic City, NJ, USA
Type
conf
DOI
10.1109/VTEST.1991.208160
Filename
208160
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