DocumentCode :
3116826
Title :
Flexible VLIW processor based on FPGA for real-time image processing
Author :
Brost, Vincent ; Meunier, Charles ; Saptono, Debyo ; Yang, Fan
Author_Institution :
LE2I, Univ. of Burgundy, Dijon, France
fYear :
2011
fDate :
2-4 Nov. 2011
Firstpage :
1
Lastpage :
8
Abstract :
Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance Very Long Instruction Word (VLIW) processor core in an FPGA. With VLIW architecture, the processor effectiveness depends on the ability of compilers to provide sufficient Instruction Level Parallelism (ILP) from program code. This paper describes research result about enabling the VLIW processor model for real-time processing applications by exploiting FPGA technology. Our goals are to keep the flexibility of processors in order to shorten the development cycle, and to use the powerful FPGA resources in order to increase real-time performance. We present a flexible VLIW VHDL processor model with a variable instruction set and a customizable architecture which allow exploiting intrinsic parallelism of a target application using advanced compiler technology and implementing it in an optimal manner on FPGA. Some common algorithms of image processing were tested and validated on an FPGA Virtex-6 based board using the proposed development cycle. Our approach applies some criteria for co-design tools: flexibility, modularity, performance, and reusability.
Keywords :
embedded systems; field programmable gate arrays; hardware description languages; image processing; instruction sets; multiprocessing systems; rapid prototyping (industrial); FPGA Virtex-6 based board; VLIW VHDL processor model; advanced compiler technology; development cycle; embedded systems; flexible VLIW processor; instruction level parallelism; memory capacity; rapid prototyping; real-time image processing; variable instruction set; very long instruction word; Computer architecture; Field programmable gate arrays; Hardware; Image processing; Registers; Signal processing algorithms; VLIW; FPGA; Rapid protoyping; VLIW processor; real-time image processing; system design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Architectures for Signal and Image Processing (DASIP), 2011 Conference on
Conference_Location :
Tampere
Print_ISBN :
978-1-4577-0620-2
Electronic_ISBN :
978-1-4577-0619-6
Type :
conf
DOI :
10.1109/DASIP.2011.6136855
Filename :
6136855
Link To Document :
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