Title :
Measuring the coverage of node shorts by internal access methods
Author :
Debany, Warren H., Jr.
Author_Institution :
Rome Lab., RL/RBRA, Griffiss AFB, NY, USA
Abstract :
A method is presented that determines the coverage of shorts (bridging failures) by internal access techniques that provide node observability such as CMOS I/sub DD/ monitoring, CrossCheck, and voltage contrast. This method requires neither fault simulation nor listing of faults, and it is exact.<>
Keywords :
CMOS integrated circuits; VLSI; fault location; integrated circuit testing; integrated logic circuits; logic testing; CMOS I/sub DD/ monitoring; CrossCheck; VLSI circuits; bridging failures; digital logic testing; internal access methods; node observability; node shorts coverage measurement; voltage contrast; CMOS logic circuits; CMOS technology; Circuit faults; Failure analysis; Fault detection; Laboratories; Logic gates; Logic testing; Power supplies; Voltage;
Conference_Titel :
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location :
Atlantic City, NJ, USA
DOI :
10.1109/VTEST.1991.208161
