Test generation techniques for sequential circuits

The authors present several methods to enhance the performance of sequential test generation algorithms. Among the innovations proposed are a new circuit model, a novel learning technique, new methods to deal with testability measures and a powerful procedure to identify untestable faults. They use an enhanced implementation of the BACK algorithm together with a set of published benchmark circuits to demonstrate the efficiency of the proposed techniques. The results show that the overall performance of the BACK algorithm is greatly improved. For many of the benchmark circuits, test generation time is reduced by more than one order of magnitude.<>