Title :
Testing the impact of process defects on ECL power-delay performance
Author :
Yuan, J.S. ; Liou, J.J. ; Wu, D.M.
Author_Institution :
Dept. of Electr. Eng., Univ. of Central Florida, Orlando, FL, USA
Abstract :
The impact of process defects on ECL power-delay product has been evaluated. The authors have developed the modeling equations including the process defects in the delay analysis. The delay equation provides the insight into the sensitivity of various process defects in ECL gate delay. The testing model equations are physics based and can be generalized to digital circuits other than ECL logic.<>
Keywords :
bipolar integrated circuits; delays; emitter-coupled logic; integrated circuit testing; integrated logic circuits; logic testing; ECL logic; ECL power-delay performance; delay analysis; digital circuits; modeling equations; process defects; testing model equations; Capacitance; Circuit optimization; Circuit testing; Current density; Delay; Equations; Integrated circuit modeling; Logic circuits; Logic testing; Voltage;
Conference_Titel :
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location :
Atlantic City, NJ, USA
DOI :
10.1109/VTEST.1991.208164
