Title :
An optimized delay testing technique for LSSD-based VLSI logic circuits
Author_Institution :
IBM VLSI Silicon, System Technol. Div., Boca Raton, FL, USA
Abstract :
In this paper, an optimized delay testing technique used in level sensitive scan design (LSSD) circuits is described. Methods of improving delay test effectiveness in four different logic groups of six LSSD test chips are illustrated. Comparison of two delay testing measurements using gross strobe timing and per-pin strobe timing are demonstrated in terms of product quality level.<>
Keywords :
VLSI; delays; integrated circuit testing; integrated logic circuits; logic testing; LSSD based circuits; VLSI logic circuits; gross strobe timing; level sensitive scan design; optimized delay testing technique; per-pin strobe timing; product quality level; Added delay; Circuit faults; Circuit testing; Delay effects; Logic circuits; Logic testing; Statistical analysis; System testing; Timing; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location :
Atlantic City, NJ, USA
DOI :
10.1109/VTEST.1991.208165
