Title :
At-speed testing of ASICs
Author :
Gauthron, Christophe
Author_Institution :
VLSI Technol. Inc., San Jose, CA, USA
Abstract :
Testing ASICs ´at-speed´ attempts to improve the test quality by detecting delay-faults. In this paper a methodology to generate at-speed test vectors is described. It is based on the comparison of simulation traces obtained within different timing conditions. The methodology has been automated and successfully used.<>
Keywords :
application specific integrated circuits; automatic testing; digital integrated circuits; fault location; integrated circuit testing; integrated logic circuits; logic testing; ASICs; at-speed test vectors; delay-faults; testing; Application specific integrated circuits; Circuit faults; Circuit testing; Clocks; Fixtures; Microwave integrated circuits; Propagation delay; System testing; Timing; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location :
Atlantic City, NJ, USA
DOI :
10.1109/VTEST.1991.208166
