Testing of VLSI CMOS System/390 processor at card and system level

Author

Hartmann, Wilfred ; Starke, Cordt W.

Author_Institution

IBM Data Syst. Div., Boeblingen, Germany

fYear

1991

fDate

15-17 April 1991

Firstpage

265

Lastpage

270

Abstract

The authors describe the design for testability (DFT) and testing methodology for the S/390 processor being part of IBM´s low-end ES/9000 systems. The design incorporates built-in pseudo-random pattern self test and the boundary scan technique. Self test permits the migration of tests generated for the component level to higher-level packages such as printed circuit boards and the system. Consequently, the expense for testing of higher-level packages has been drastically reduced and the card test equipment can be simplified. In addition, the applied strategy offers economical diagnostic capability.<>

Keywords

CMOS integrated circuits; IBM computers; VLSI; built-in self test; computer testing; integrated circuit testing; logic design; logic testing; BIST; S/390 processor; VLSI CMOS; boundary scan technique; card level testing; design for testability; diagnostic capability; pseudo-random pattern self test; system level; testing methodology; Automatic testing; Built-in self-test; CMOS process; Circuit testing; Costs; Design for testability; Logic testing; Packaging machines; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers

Conference_Location

Atlantic City, NJ, USA

Type

conf

DOI

10.1109/VTEST.1991.208169

Filename

208169