Title :
Evaluation of detectability in BIST environment
Author :
Feng, Sheng ; Malaiya, Yashwant K.
Author_Institution :
Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO, USA
Abstract :
Built-in self-test (BIST) technique is now widely applied. How to estimate its testing capabilities is an important problem. BIST detectability is defined as the probability of that a fault set of the circuit-under-test is detected. It depends on the properties of the test at, circuit-under-test, as well as the signature analyser as a data compressor. The detectability of a signature analyzer is evaluated. The random and pseudorandom testing techniques are examined for their BIST detectability and several results are derived.<>
Keywords :
automatic testing; built-in self test; integrated circuit testing; logic testing; probability; BIST detectability; BIST environment; data compressor; detectability evaluation; fault set; probability; pseudorandom testing; random testing; signature analyser; testing capabilities; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Computer science; Data analysis; Electrical fault detection; Fault detection; Polynomials; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location :
Atlantic City, NJ, USA
DOI :
10.1109/VTEST.1991.208170
