Title :
Efficient test generation for built-in self-test boundary-scan template
Author :
Nagvajara, P. ; Karpovsky, M.G. ; Levitin, L.B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA, USA
Abstract :
An analysis and design of a pseudorandom pattern generator, (PRPG), based on a linear recurrence, for built-in self-test (BIST) boundary scan design is presented. The authors present for the case when r>or=s, a design of an s-stage PRPG capable of producing 2/sup s/-1 distinct r-bit patterns within 2/sup s/-1 clock pulses independent of the hardware realization of the PRPG. For the case when r>
Keywords :
built-in self test; integrated circuit testing; logic testing; BIST; boundary-scan template; built-in self-test; clock pulses; linear recurrence; pseudorandom pattern generator; test generation; Automatic testing; Built-in self-test; Circuit testing; Clocks; Design engineering; Laboratories; Pattern analysis; Pulse generation; System testing; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location :
Atlantic City, NJ, USA
DOI :
10.1109/VTEST.1991.208171
