Title :
Test pattern generation for current testable faults in static CMOS circuits
Author :
Ferguson, F. Joel ; Larrabe, Tracy
Author_Institution :
Comput. Eng. Board of Studies, California Univ., Santa Cruz, CA, USA
Abstract :
Many manufacturing defects in static CMOS circuits are not detected by tests generated using the traditional single stuck-at fault model. May of these defects may be detected as increased propagation time or as excessive quiescent power supply current (IDDQ). In this paper the authors consider the probable manufacturing defects and compare the costs of detecting them by the resulting excess IDDQ versus the cost of traditional testing methods.<>
Keywords :
CMOS integrated circuits; integrated circuit testing; logic testing; IDDQ testing; current testable faults; manufacturing defects; quiescent power supply current; static CMOS circuits; Circuit faults; Circuit testing; Costs; Current supplies; Electrical fault detection; Fault detection; Power supplies; Semiconductor device modeling; Test pattern generators; Virtual manufacturing;
Conference_Titel :
VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers
Conference_Location :
Atlantic City, NJ, USA
DOI :
10.1109/VTEST.1991.208174
