Data line driver design for A 10" 480×640×3 color FED

Author

Wang, Chi-Chang ; Wu, Jiin-Chuan ; Huang, Chin-Ming

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1996

fDate

7-12 Jul 1996

Firstpage

557

Lastpage

561

Abstract

A data line driver with 120 outputs and capable of producing contrast ratio over 100 for a 10" 480×(640×3) pixels color field emission display (FED) panel have been designed. Phase clocks were used to reduce the maximum operating frequency to 22.68 MHz. A class AB op amp was used as the analog output buffer to reduce the power dissipation. The chip is implemented in a 24 V CMOS process, chip size is 7620 μm×17500 μm

Keywords

CMOS analogue integrated circuits; buffer circuits; driver circuits; flat panel displays; large screen displays; vacuum microelectronics; 10 in; 1920 pixel; 22.68 MHz; 24 V; 480 pixel; 921600 pixel; CMOS process; analog output buffer; class AB op amp; color field emission display panel; contrast ratio; data line driver; large flat panel displays; maximum operating frequency; power dissipation; Anodes; Brightness; CMOS process; Cathodes; Driver circuits; Electronics industry; Flat panel displays; Industrial electronics; Liquid crystal displays; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Vacuum Microelectronics Conference, 1996. IVMC'96., 9th International

Conference_Location

St. Petersburg

Print_ISBN

0-7803-3594-5

Type

conf

DOI

10.1109/IVMC.1996.601886

Filename

601886

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=311709