Constraints for using IDDQ testing to detect CMOS bridging faults

Author

Lee, Kuen-Jong ; Breuer, Melvin A.

Author_Institution

Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

1991

fDate

15-17 April 1991

Firstpage

303

Lastpage

308

Abstract

Detecting CMOS bridging faults (BFs) using IDDQ testing, or the current supply monitoring method (CSM), has recently received much attention. One fundamental question that needs to be answered for this technique is ´what circuits does it apply to´. Previously the authors presented a set of constraints on circuits and their test environment that formed a sufficient condition for using CSM to detect all single and multiple irredundant BFs. In this paper they show that if any of these constraints are removed then circuits exist for which CSM cannot give correct results. Two special classes of circuits, domino logic and synchronous sequential circuits, are discussed in detail.<>

Keywords

CMOS integrated circuits; fault location; integrated circuit testing; integrated logic circuits; logic testing; sequential circuits; CMOS bridging faults; IDDQ testing; current supply monitoring method; domino logic; synchronous sequential circuits; CMOS logic circuits; Circuit faults; Circuit testing; Condition monitoring; Current supplies; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Steady-state;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers

Conference_Location

Atlantic City, NJ, USA

Type

conf

DOI

10.1109/VTEST.1991.208175

Filename

208175