Logic characteristics of 40 nm thin-channel InAs HEMTs

We have experimentally investigated the trade-offs involved in thinning down the channel of III-V FETs with the ultimate goal of enhancing the electrostatic integrity and scalability of these devices. To do so, we have fabricated InAs HEMTs with a channel thickness of t_ch = 5 nm and we have compared them against, InAs HEMTs with t_ch = 10 nm. The fabricated thin-channel devices exhibit outstanding logic performance and scalability down to 40 nm in gate length. L_g = 40 nm devices exhibit S = 72 mV/dec, DIBL = 72 mV/V, and I_ON/I_OFF = 2.5 × 10⁴, all at V_DS = 0.5 V. However, there are trade-offs of using a thin channel which manifest themselves in a higher source resistance, lower transconductance, and lower f_T when compared with InAs HEMTs with t_ch = 10 nm.