A low-power CMOS-VLSI circuit for signal conditioning in integrated capacitive sensors

Capacitive sensor manufacturing processes are rarely compatible with CMOS technologies and, thus, monolithic integration of sensing device and signal-conditioning IC is often not possible. Multi-chip packaging and wire bonding is employed instead, to interconnect sensor and IC dies. In such cases, sensor capacitance is comparable or even smaller than the parasitic interconnection capacitance, while interconnection parasitic resistance inserts additional signal distortion. The signal-conditioning IC must be designed to compensate for these parasitic effects. Switched-capacitor ICs may fulfil such specifications but the use of several operational amplifiers and intricate clocking schemes increase design complexity, die-size, and power consumption, which is inappropriate for wireless applications. In this work a low-power switched-capacitor IC for sub-fF capacitance measurements is presented. The proposed design requires two non-overlapping clocks but no operational amplifiers. It shows excellent robustness against interconnection parasitics, transistor dimensional mismatches, temperature, and process variations.