NBTI aging tolerance in pipeline based designs NBTI

Aging mechanisms, like Negative Bias Temperature Instability (NBTI), are a great concern in CMOS nanometer technologies. In this work, we present pipeline oriented timing error tolerance techniques with a special interest in NBTI related performance degradation. Three scenarios are discussed that provide the required error tolerance in pipeline based designs. Moreover, a new flip-flop is presented, to support two of the above scenarios, which is capable to detect and locally correct timing errors. A main characteristic of the proposed flip-flop is the NBTI resistant error handling operation. Simulation results validate the efficiency of the new design.