Development and integration of applique decoupling capacitors

For high-speed integrated circuit applications, it is important to interconnect decoupling capacitors and integrated circuits (ICs) as intimately as possible, to minimize parastic impedances. This can be achieved by mounting freestanding, thin film capacitors directly onto ICs as part of a chip-scale packaging approach. These “applique” capacitors utilize a chemically-prepared PLZT dielectric, which is nominally 1 μm thick. The small size and weight of applique capacitors can be used to improve packaging efficiency. Applique capacitors, which are initially fabricated on silicon wafers, have high permittivity (ε≅1000), low loss (tanδ≅0.01) and high breakdown strength (E_B≅1 MV/cm) and leakage resistance (ρ>10¹⁴ Ω-cm @ 125°C). Various processes being developed to remove the capacitors from the silicon substrate and reattach them to ICs are described. In addition, a concept for interconnecting the capacitors using a repatterning process is discussed