DocumentCode :
3117740
Title :
At-speed BIST for interposer wires supporting on-the-spot diagnosis
Author :
Shi-Yu Huang ; Jeo-Yen Lee ; Kun-Han Tsai ; Wu-Tung Cheng
Author_Institution :
Electr. Eng. Dept., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear :
2013
fDate :
8-10 July 2013
Firstpage :
67
Lastpage :
72
Abstract :
Testing the speed of post-bond interposer wires in a 2.5-D stacked IC is essential for silicon debugging, yield learning, and even for fault tolerance. In this paper, we present a novel at-speed test technique called Pulse-Vanishing test (PV-test), in which a short-duration pulse signal is applied to an interposer wire under test at the d river end. If the pulse signal can successfully propagate through the interposer wire and reach the other end, then the interposer wire is considered fault-free. Otherwise, it indicates the presence of a delay fault. This new test technique has several technical merits. For example, the Design-for-Testability (DfT) circuit for an interposer wire is similar to the boundary scan cell and can be controlled through scan chain. Also, it can be easily adapted to perform at-speed Built-In Self-Test (BIST) supporting on-the-spot diagnosis.
Keywords :
built-in self test; design for testability; fault tolerance; integrated circuit testing; 2.5-D stacked IC; BIST; DfT; PV-test; at-speed GIST; built-in self-test; delay fault; design-for-testability circuit; fault tolerance; on-the-spot diagnosis; post-bond interposer wires; pulse-vanishing test; short-duration pulse signal; silicon debugging; yield learning; Control systems; Decision support systems; Receivers; Silicon; Testing; Wires; 2.5-D Stacked IC; At-Speed Test; Built-In Self-Test; Delay Fault; Interposer; Post-bond Test; Pulse-Vanishing Test;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2013 IEEE 19th International
Conference_Location :
Chania
Type :
conf
DOI :
10.1109/IOLTS.2013.6604053
Filename :
6604053
Link To Document :
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