New technology and tool for enhanced packaging of semiconductor power devices

This paper presents a novel interconnect technology and packaging solution for silicon power devices, along with the virtual prototyping tool created to develop the concept and optimize it in terms of reliability. The technology is based on the use of bumps (i.e., conductive spheres or cylinders) to connect the surface of vertical power components and is characterized, in comparison with standard bond-wire technology, by reduced stray inductance (i.e., better performance), higher integration levels (i.e., higher power density) and double-sided chip cooling capability (i.e., improved efficiency), key aspects in power electronics technology evolution. The tool exemplifies an innovative methodology for using multi-domain multi-level abstraction simulation as the principal instrument of iterative design and optimization, enabler for competitive development of novel power technologies.