Test chip characterization of X architecture diagonal lines for SoC design

This paper addresses the manufacturability, yield and reliability aspects of an X architecture (diagonal lines) silicon-on-chip (SoC) design that enables IC chips to become faster and smaller (area) compared to the same design in a Manhattan structure. Test chips that consist of comb/serpentine, maze, via chain, as well as resistance and capacitance structures are designed and fabricated using both a 130 nm and a 90 nm copper CMOS processes. The measurements of the line resistance (Kelvin structures), capacitance (inter-digited structure) and SEM data show that for 1:1 design rules (Manhattan vs. X architecture), the uniformity and fidelity of the diagonal lines are as good as Manhattan lines. The current generation of mask, lithography, and wafer processing techniques are applicable to X architecture designs.