Title :
A 50 MIPS multiprocessor chip for image processing
Author :
Denayer, T. ; Vanzieleghem, E. ; Jespers, P.
Author_Institution :
Lab. de Microelectron., Univ. Catholique de Louvain, Belgium
Abstract :
A 50-MIPS (million-instruction-per-second) 90000-transistor CMOS multiprocessor chip is described. It has been designed as a building block for orthogonal transforms of TV images in a bandwidth-reduction system. 64 processing elements (serial parallel multipliers) are assembled in a systolic-like architecture. Because of its modularity, the chip can be used for matrix products of arbitrary size
Keywords :
CMOS integrated circuits; cellular arrays; computerised picture processing; microprocessor chips; multiprocessing systems; telecommunications computing; 50 MIPS; CMOS multiprocessor chip; TV images; bandwidth-reduction system; computerised picture processing; image processing; matrix products; modularity; orthogonal transforms; serial parallel multipliers; systolic-like architecture; Bandwidth; Computer architecture; Discrete cosine transforms; Discrete transforms; Frequency; Image coding; Image processing; Pipelines; Shift registers; TV;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20823
