Parity check for m-of-n delay insensitive codes

The advance in deep submicron technologies brings new constraints to circuit design such as variability and sensitivity to soft errors. Asynchronous networks on chip can help coping with some of these constraints due to the timing robustness of design paradigms such as the quasi delay insensitive one. A relevant problem of current fully asynchronous networks on chip is the lack of mechanisms to provide error detection and correction in asynchronous data communication. This work proposes a parity scheme applicable to m-of-n delay insensitive codes, which is capable to correct errors caused by single event effects in delay insensitive communication architectures. The proposed mechanism was evaluated in a 65nm technology where it is able to correct 98% of the errors caused by single event effects with a low overhead in terms of area, power and performance.