A novel test-structure for detail interconnect fabric diagnosis for 90nm process

Using low-k materials is one of the important new technologies to improve circuit performance in capacitive-load rich interconnect fabric. However, it is very difficult to measure the permittivity of the low-k material in actual small pitched wires, including its statistical distribution within the die and wafer. We have already developed a technology to evaluate ILD (inter layer dielectric) dimensions by using special test-structures named ILDEx. This test-structure is used to extract ILD dimensions with capacitance measurement. The basic idea is a systematic electrical characterization of densely-pitched interconnect fabric accompanied with a CAD tool which conducts intensive 3D capacitance computation and a new ILD-data extraction algorithm. However, the ILDEx test-structure needs a specific layout area to get 10-100 fF capacitance as well as additional de-embedding patterns. In this work, we present a newly developed multi-layer ILDEx test-structure with a CBCM circuit, which results in a compact and accurate extraction of ILD dimensions.