Design and implementation of a two-dimensional fast Fourier transform chip

A description is given of a rasterized, pipelined architecture for performing a two-dimensional fast Fourier transformation (2DFFT). A chip has been designed for implementing this architecture in 1.25-μm CMOS. Each chip consist of 152 transistors on a 9-mm die. The chips operate at a clock speed of 10 MHz and process a 256×256-pixel image at a real-time rate of 30 Hz. Each chip has input and output data formats consisting of rasterized streams of 22-bit fixed-point complex numbers. The authors present the chip architecture and describe the design of its constituent units. On-chip storage of the sine/cosine factors and the absence of corner-tuning memory are the most novel features