A radiation tolerant and self-repair memory cell

In this paper a new radiation tolerant memory cell is proposed. As CMOS technologies scale down, existing hardened cells, which are technology dependent, become more and more vulnerable to radiation effects. We tested some of the most known and effective hardened cells using the SPICE simulator LTspice but no one proved to ensure data integrity. The proposed cell consists of three standard 6T cells and proves to be 100% radiation tolerant in any technology, having however an expected area and power overhead comparing to the 6T and DICE cells. According to simulation results, these overheads are proportional to the number of transistors used, but the read time when no error has occurred and the write time are shorter.