Title :
The architectures and design of a 20-MHz real-time DSP
Author :
Ruetz, Peter A. ; Ang, Peng H.
Author_Institution :
LSI Logic Corp., Palo Alto, CA, USA
Abstract :
A set of four real-time 20-MHz digital signal processor (DSP) chips have been designed, fabricated, and tested. The chips include a 64-tap programmable FIR (finite-impulse response) filter, a 1024-tap binary filter and template matcher, a 64-tap rank-value filter, and an eight-line 512-pixel video-line delay. All of the circuits were implemented in a 1.5-μm CMOS process and are fully functional with a 20-MHz clock rate
Keywords :
CMOS integrated circuits; computer architecture; computerised picture processing; digital filters; microprocessor chips; 1024-tap binary filter; 20 MHz; 512 pixel; 64-tap rank-value filter; computerised picture processing; digital signal processor; finite impulse response filter; microprocessor chips; template matcher; video-line delay; CMOS process; Circuit testing; Clocks; Delay; Digital signal processing; Digital signal processing chips; Digital signal processors; Finite impulse response filter; Matched filters; Signal design;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20825
