A programmable analog neural network chip

Analog VLSI implementations of adaptive systems, either of the traditional variety or the more complex types frequently found in neural network models of learning, require variable analog weights which are compact and have substantial resolution. The authors have designed a chip in ordinary 1.25- μm CMOS which stores analog weights as charge on MOS capacitors. The weights, of which there are 1104 per chip, can be updated in parallel along a vector in weight space, allowing for efficient implementations of gradient descent algorithms. The chips are organized as 46×24 matrix multipliers with voltage inputs and current outputs