A new multi-algorithm multichannel cascadable digital filter processor

Author

Lin, John ; Lewis, Larry ; Lee, Keith

Author_Institution

Fujitsu Microelectron. Inc., Santa Clara, CA, USA

fYear

1988

fDate

16-19 May 1988

Abstract

A description is given of the MB86975 adaptive filter processor (AFP), an application-specific processor for digital filtering. The AFP operates autonomously and does not need to be under control of a host processor during filter operations. It has been designed and fabricated in 1.8- μm CMOS standard cell technology with a total gate count of 14,000 and worst-case power dissipation of 500 mW. The AFP is packaged in a 68-pin LCC (leaded chip carrier) package. The AFP clock operates at 10 MHz with one clock per FIR (finite-impulse response) tap, two clocks per LMS (least-mean square) tap, and five clocks per IIR (infinite-impulse response) biquad. The AFP implements the most commonly used and most well understood digital filter algorithms-FIR, IIR, and LMS

Keywords

CMOS integrated circuits; digital filters; microprocessor chips; signal processing equipment; 1.8 micron; 10 MHz; CMOS standard cell technology; MB86975 adaptive filter processor; application-specific processor; digital filter algorithms; finite-impulse response; infinite-impulse response; leaded chip carrier package; least-mean square; multi-algorithm multichannel cascadable digital filter processor; Adaptive filters; Application specific processors; CMOS technology; Clocks; Digital filters; Filtering; Finite impulse response filter; Least squares approximation; Packaging; Page description languages;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/CICC.1988.20842

Filename

20842