A new multi-algorithm multichannel cascadable digital filter processor

A description is given of the MB86975 adaptive filter processor (AFP), an application-specific processor for digital filtering. The AFP operates autonomously and does not need to be under control of a host processor during filter operations. It has been designed and fabricated in 1.8- μm CMOS standard cell technology with a total gate count of 14,000 and worst-case power dissipation of 500 mW. The AFP is packaged in a 68-pin LCC (leaded chip carrier) package. The AFP clock operates at 10 MHz with one clock per FIR (finite-impulse response) tap, two clocks per LMS (least-mean square) tap, and five clocks per IIR (infinite-impulse response) biquad. The AFP implements the most commonly used and most well understood digital filter algorithms-FIR, IIR, and LMS