DocumentCode
3119058
Title
A novel parasitic insensitive switched-capacitor technique for realizing very large time constants
Author
Nagaraj, K.
Author_Institution
AT&T Bell Labs., Murray Hill, NJ, USA
fYear
1988
fDate
16-19 May 1988
Abstract
A novel technique for realizing very large time constant switched-capacitor integrators is presented. The integrators are area-efficient and are insensitive to parasitic capacitances. A 60-Hz notch filter working from a 128-kHz clock has been designed using these integrators and implemented in a 1.5 μm CMOS technology
Keywords
CMOS integrated circuits; switched capacitor networks; 1.5 micron; 128 kHz; 60 Hz; notch filter; switched-capacitor integrators; Analog integrated circuits; Attenuation; CMOS technology; Clocks; Filters; Frequency; Integrated circuit technology; Parasitic capacitance; Poles and zeros; Switched capacitor circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/CICC.1988.20852
Filename
20852
Link To Document