DocumentCode
3119098
Title
Impact of pocket implant on MOSFET mismatch for advanced CMOS technology
Author
Mc Ginley, J. ; Noblanc, O. ; Julien, C. ; Parihar, S. ; Rochereau, K. ; Difrenza, R. ; Llinares, P.
Author_Institution
Motorola Inc, Crolles, France
fYear
2004
fDate
22-25 March 2004
Firstpage
123
Lastpage
126
Abstract
This paper deals with MOS transistors mismatch for advanced 120 nm and 90 nm CMOS technologies. In particular we demonstrate pocket implant impact on the gate contribution that becomes more and more important with the gate oxide thickness reduction. Such a phenomenon can appear as a limit for matching improvement with CMOS technologies evolution.
Keywords
CMOS integrated circuits; MOSFET; dielectric thin films; doping profiles; integrated circuit design; ion implantation; 120 nm; 90 nm; CMOS technology; MOS transistors; MOSFET mismatch; gate contribution; gate oxide thickness reduction; matching improvement limit; pocket implant; CMOS technology; Circuit synthesis; Fluctuations; Geometry; Implants; MOS devices; MOSFET circuits; Semiconductor device modeling; Technology forecasting; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on
Print_ISBN
0-7803-8262-5
Type
conf
DOI
10.1109/ICMTS.2004.1309464
Filename
1309464
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