Design and measurements of test element group wafer thinned to 10 μm for 3D system in package

Author

Ikeda, Akihiro ; Kuwata, Tomonori ; Kajiwara, Satoru ; Fujimura, Tsuyoshi ; Kuriyaki, Hisao ; Hattori, Reiji ; Ogi, Hiroshi ; Hamaguchi, Kiyoshi ; Kuroki, Yukinori

Author_Institution

Dept. of Electron., Kyushu Univ., Fukuoka, Japan

fYear

2004

fDate

22-25 March 2004

Firstpage

161

Lastpage

164

Abstract

We designed and measured test element group wafers thinned to 10 μm for 3D system in package. The n-well p-Si diodes in 10 μm thick wafer showed increasing of the reverse saturation current in comparison to the currents in 20 μm, 30 μm or 640 μm thick wafer. While the pMOSFETs and nMOSFETs in 10 μm thick wafer showed no degradation of mobility, sub-threshold swing and threshold voltage. Defects might be induced by mechanical stress during wafer back grinding process near wafer back side, within a few micron-meters from the wafer back surface.

Keywords

CMOS logic circuits; chip scale packaging; flip-chip devices; integrated circuit measurement; integrated circuit testing; 10 micron; 3D system in package; CMOS inverters; I-V curves; bump interconnections; chip level stacking; chip-level packaging; flip-chip bump; inverter chain; mechanical stress; n-well p-Si diodes; nMOSFET; pMOSFET; reverse saturation current; test element group wafer; wafer back grinding; wafer thinning; Conductivity; Electronics packaging; Flip chip; Integrated circuit interconnections; MOSFETs; Mechanical variables measurement; Semiconductor device measurement; Stacking; Stress; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 2004. Proceedings. ICMTS '04. The International Conference on

Print_ISBN

0-7803-8262-5

Type

conf

DOI

10.1109/ICMTS.2004.1309471

Filename

1309471