Test Patterns for Verilog Design Error Localization

In this article we briefly state the idea behind model-based diagnosis and its application to debugging RTL (Register Transfer Level) Verilog designs. In providing a debugging model for the Verilog HDL (Hardware Description Language) we rely on a specific abstraction (trace semantics) that captures solely quiescent states of the design. In this vein we manage to overcome the inherent complexity issues of event-based Verilog without relying on specific fault models. To leverage test patterns for design error localization we propose the filtering approach and relate it to the concept of Ackermann constraints. Notably, our empirical results demonstrate that our novel technique considerably increases the diagnosis resolution even under presence of only a couple of test cases. The article outlines a case study comprising several circuits, where the proposed technique allowed one for excluding 95 per cent of the Verilog code from being faulty by merely considering a couple of test cases.